SI5347D-D-GM OverviewThis clock IC is packaged using the Tray method. The 64-VFQFN Exposed Pad package includes this clock generator. In it, there are 64 terminations to be found. This time clock generator should be voltaged at 1.8V. A clock generator's input is called LVCMOS, LVDS, LVPECL, Crystal and it is designed as the input for this clock generator. For full access to the electronic component's capabilities, 1 circuits are implemented. A clock-based RF synthesizer that provides a max frequency of 350MHz is available. With the Surface Mount, it is easy to install this electric component on the panel. The digital clock generator incorporates CLOCK GENERATOR, PROCESSOR SPECIFIC uPs, uCs, and peripheral ICs. This clock PLL works with a supply voltage of 1.71V~3.47V. Using the test statistics, it is estimated that the ambient temperature should be set to -40°C~85°C. A frequency synthesizer which is compatible with the CML, HCSL, LVCMOS, LVDS, LVPECL logic levels is presented here. The frequency generator has a ALSO REQUIRES 3.3V SUPPLY feature to improve the output of clock signals.
SI5347D-D-GM FeaturesAvailable in the 64-VFQFN Exposed Pad
Supply voltage of 1.8V
SI5347D-D-GM ApplicationsThere are a lot of Silicon Labs
SI5347D-D-GM Clock Generators applications.
Digital circuits
Wireless base station for LTE, LTE-advanced
Picocells, femtocells and small cells
Sampling clocks for ADC and DAC
1 Gigabit Ethernet
10 Gigabit Ethernet
FPGA and processor clocks
Line cards used in telephone exchange
Fiber Channel
PCI express cards
Factory Lead Time | 6 Weeks |
Mounting Type | Surface Mount |
Package / Case | 64-VFQFN Exposed Pad |
Surface Mount | YES |
Operating Temperature | -40°C~85°C |
Packaging | Tray |
Published | 2016 |
Pbfree Code | yes |
Part Status | Active |
Moisture Sensitivity Level (MSL) | 2 (1 Year) |
Number of Terminations | 64 |
ECCN Code | EAR99 |
Additional Feature | ALSO REQUIRES 3.3V SUPPLY |
Voltage - Supply | 1.71V~3.47V |
Terminal Position | QUAD |
Terminal Form | NO LEAD |
Supply Voltage | 1.8V |
Terminal Pitch | 0.5mm |
Output | CML, HCSL, LVCMOS, LVDS, LVPECL |
JESD-30 Code | S-XQCC-N64 |
Number of Circuits | 1 |
uPs/uCs/Peripheral ICs Type | CLOCK GENERATOR, PROCESSOR SPECIFIC |
Frequency (Max) | 350MHz |
Input | LVCMOS, LVDS, LVPECL, Crystal |
Ratio - Input:Output | 5:4 |
Primary Clock/Crystal Frequency-Nom | 54MHz |
PLL | Yes |
Differential - Input:Output | Yes/Yes |
Divider/Multiplier | Yes/No |
Length | 9mm |
Height Seated (Max) | 0.9mm |
Width | 9mm |
RoHS Status | Non-RoHS Compliant |