SI5382E-E-GMR OverviewIt is packaged using the Tape & Reel (TR) method since it is a clock IC. Embedded in the 64-VFQFN Exposed Pad package is this Clock PLL. Frequency generator is capable of operating at a maximum temperature of NOT SPECIFIED when reflowing. It is designed that the Clock PLL's input should be LVCMOS, Crystal. A total of 2 circuits are implemented to access the full performance of the electrical part. Using this clock-based frequency synthesizer, you can achieve a maximum frequency of 735MHz 2.94912GHz. Because of the Surface Mount, clock PLL can be easily mounted on the panel. As long as you provide 1.71V~3.47V supply voltage, it will work. Using the test statistics, we estimate that the ambient temperature should be -40°C~85°C. The RF synthesizer is compatible with HCSL, LVCMOS, LVDS, LVPECL logic levels. An electrical part such as this one can be classified as a Clock Jitter Attenuator component.
SI5382E-E-GMR FeaturesAvailable in the 64-VFQFN Exposed Pad
SI5382E-E-GMR ApplicationsThere are a lot of Silicon Labs
SI5382E-E-GMR Clock Generators applications.
1 Gigabit Ethernet
10 Gigabit Ethernet
FPGA and processor clocks
Line cards used in telephone exchange
Fiber Channel
PCI express cards
Infotainment systems
Medical equipment
Multi-function printers
Media broadcast servers
Mounting Type | Surface Mount |
Package / Case | 64-VFQFN Exposed Pad |
Operating Temperature | -40°C~85°C |
Packaging | Tape & Reel (TR) |
Part Status | Obsolete |
ECCN Code | EAR99 |
Type | Clock Jitter Attenuator |
Voltage - Supply | 1.71V~3.47V |
Peak Reflow Temperature (Cel) | NOT SPECIFIED |
Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
Output | HCSL, LVCMOS, LVDS, LVPECL |
Number of Circuits | 2 |
Frequency (Max) | 735MHz 2.94912GHz |
Input | LVCMOS, Crystal |
Ratio - Input:Output | 4:12 |
PLL | Yes |
Differential - Input:Output | Yes/Yes |
Divider/Multiplier | Yes/No |
RoHS Status | RoHS Compliant |