9DBL1200AGLF Overview
In order to ensure the safety and security of the product, it is packaged in a case with a TFSOP-serial number. This termination has 64 terminations. 3.3V is the voltage provided by this part. 260 runs using this part's peak reflow temperature. In the device, there are 1. Clock program is normalfor the operation frequency to be 400MHz. Vsup reaches 3.465V at its maximum. A total of 2013 publications have been made of the part. With Surface Mount, it is recommended that it be mounted. Minimum working temperature must not be below 0°C. Temperatures below 70°C should be used. If you choose a part from the 9DBL family, you can find parts that are related to that part.
9DBL1200AGLF Features
Peak Reflow Temperature (Cel): 260
Include 1 Circuits

9DBL1200AGLF Applications
There are a lot of Integrated Device Technology (IDT)
9DBL1200AGLF application specific timer applications.

Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fibre Channel, SAN
Telecom line cards
1 GbE and 10 GbE
Servers, Storage, Search Acceleration
Ethernet Switches, Routers
Small Cells, Mobile Backhaul/Fronthaul
Print Imaging

Mount	Surface Mount
Package / Case	TFSOP
Published	2013
JESD-609 Code	e3
Number of Terminations	64
Terminal Finish	Matte Tin (Sn)
Max Operating Temperature	70°C
Min Operating Temperature	0°C
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Number of Functions	1
Supply Voltage	3.3V
Terminal Pitch	0.5mm
Time@Peak Reflow Temperature-Max (s)	30
JESD-30 Code	R-PDSO-G64
Supply Voltage-Max (Vsup)	3.465V
Power Supplies	3.3V
Temperature Grade	COMMERCIAL
Number of Circuits	1
Frequency (Max)	400MHz
Family	9DBL
Output Characteristics	3-STATE
Input	Clock
Max I(ol)	0.25 A
PLL	No
Same Edge Skew-Max (tskwd)	0.05 ns
Number of True Outputs	24
RoHS Status	RoHS Compliant