| Factory Lead Time | 10 Weeks |
| Contact Plating | Copper, Silver, Tin |
| Mount | Surface Mount |
| Package / Case | 484-LFBGA, CSPBGA |
| Number of Pins | 485 |
| Operating Temperature | 0°C~100°C TJ |
| Packaging | Tray |
| Series | Zynq®-7000 |
| Published | 2010 |
| JESD-609 Code | e1 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 485 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| Additional Feature | PL BLOCK OPERATES IN 0.97V TO 1.03V SUPPLY |
| HTS Code | 8542.39.00.01 |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1V |
| Terminal Pitch | 0.8mm |
| Frequency | 766MHz |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 1.05V |
| Power Supplies | 11.8V |
| Supply Voltage-Min (Vsup) | 0.95V |
| Interface | CAN, EBI/EMI, Ethernet, I2C, MMC, SD, SDIO, SPI, UART, USART, USB |
| Number of I/O | 130 |
| RAM Size | 256KB |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR CIRCUIT |
| Core Processor | Dual ARM® Cortex®-A9 MPCore™ with CoreSight™ |
| Peripherals | DMA |
| Connectivity | CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SPI, UART/USART, USB OTG |
| Architecture | MCU, FPGA |
| Data Bus Width | 32b |
| Core Architecture | ARM |
| Boundary Scan | YES |
| RAM (words) | 256000 |
| Primary Attributes | Artix™-7 FPGA, 74K Logic Cells |
| Bus Compatibility | CAN; ETHERNET; I2C; SPI; UART; USB |
| UV Erasable | N |
| Length | 19mm |
| Height Seated (Max) | 1.6mm |
| RoHS Status | ROHS3 Compliant |
XC7Z015-2CLG485E Datasheet
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