CY37128P84-125JXI OverviewThis network has 128macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).You can find it in package 84-LCC (J-Lead).As a result, it has 69 I/O ports programmed.84 terminations have been programmed into the device.Its terminal position is QUAD.It is powered by a voltage of 5V volts.Package the chip by Tube.In order to ensure the reliability of the device, it is designed to operate at a temperature of [0].Chips should be mounted by Surface Mount.In terms of FPGAs, it belongs to the Ultra37000™ series.It has 84 pins programmed.Its related parts can be found in the [0].The 3800 gates serve as building blocks for digital circuits.It is recommended that the supply voltage be kept at 5Vto maximize efficiency.It is adopted to store data in EEPROM.The electronic component is mounted by Surface Mount.There are 84 pins on the device.In this case, the maximum supply voltage is 5.5V.Despite its minimal supply voltage of 4.5V, it is capable of operating.In this case, 125MHz is the frequency that can be achieved.There are 8 logic blocks (LABs) in its basic building block.Input signals are detected by 1 dedicated inputs.
CY37128P84-125JXI Features84-LCC (J-Lead) package
69 I/Os
The operating temperature of -40°C~85°C TA
84 pin count
84 pins
8 logic blocks (LABs)
CY37128P84-125JXI ApplicationsThere are a lot of Cypress Semiconductor Corp
CY37128P84-125JXI CPLDs applications.
Discrete logic functions
Bootloaders for FPGAs
Address decoders
Custom state machines
Digital systems
Portable digital devices
Handheld digital devices
Battery operated portable devices
Complex programmable logic devices
Digital designs
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 84-LCC (J-Lead) |
| Number of Pins | 84 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | Ultra37000™ |
| Published | 2003 |
| JESD-609 Code | e3 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 84 |
| Terminal Finish | Matte Tin (Sn) |
| Terminal Position | QUAD |
| Terminal Form | J BEND |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Terminal Pitch | 1.27mm |
| Frequency | 125MHz |
| Time@Peak Reflow Temperature-Max (s) | 20 |
| Base Part Number | CY37128 |
| Pin Count | 84 |
| Operating Supply Voltage | 5V |
| Programmable Type | In-System Reprogrammable™ (ISR™) CMOS |
| Max Supply Voltage | 5.5V |
| Min Supply Voltage | 4.5V |
| Number of I/O | 69 |
| Memory Type | EEPROM |
| Propagation Delay | 10 ns |
| Turn On Delay Time | 10 ns |
| Number of Gates | 3800 |
| Number of Logic Blocks (LABs) | 8 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| Number of Dedicated Inputs | 1 |
| Voltage Supply - Internal | 4.5V~5.5V |
| Length | 29.3116mm |
| Width | 29.3116mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CY37128P84-125JXI Datasheet
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