DS1005M-125+ OverviewFor cost-effectiveness, it is packaged using Tube. 8-DIP (0.300, 7.62mm) packages eliminate the need for additional insulating hardware in applications. Reliable performance is ensured by the supply voltage of 4.75V~5.25V. It is mounted using the technique of Through Hole. The device features an operating temperature of 0°C~70°C. The device is configured with 5 taps/steps. For a wide range of applications, related parts with the same base part number DS1005 are universally preferred. DUAL is the location of the terminals. For unique configurations, it is equipped with 8 terminations. When the device is operating, it is supplied with a voltage of 5V. Its logic type is SILICON DELAY LINE. In order to ensure flexible operation, 5V is equipped with a power supply. The compound is a key component of the CMOS/TTL family.
DS1005M-125+ FeaturesSupply voltage at Tube volts
operate supply current at 5V
with SILICON DELAY LINE bits
supply type: 5V
stay resistance at CMOS/TTL
DS1005M-125+ ApplicationsThere are a lot of Maxim Integrated
DS1005M-125+ Delay Lines Timing ICs applications.
Delay Matching
Switch Debouncing
High Vibration, High Acceleration Environments
Portable and Battery-Powered Equipment
Clock Synchronization
Digital Systems
Embedded Systems
Utility Meters
Security Systems
Network Hubs, Bridges, and Routers
| Mounting Type | Through Hole |
| Package / Case | 8-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | 0°C~70°C |
| Packaging | Tube |
| Published | 1999 |
| JESD-609 Code | e3 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Terminal Finish | Matte Tin (Sn) |
| Voltage - Supply | 4.75V~5.25V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | DS1005 |
| JESD-30 Code | R-PDIP-T8 |
| Function | Nonprogrammable |
| Qualification Status | Not Qualified |
| Power Supplies | 5V |
| Family | CMOS/TTL |
| Output Polarity | TRUE |
| Logic IC Type | SILICON DELAY LINE |
| Number of Taps/Steps | 5 |
| Number of Independent Delays | 1 |
| Delay to 1st Tap | 25ns |
| Programmable Delay Line | NO |
| Available Total Delays | 125ns |
| Total Delay-Nom (td) | 125 ns |
| Width | 7.62mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |