DS1013-75 OverviewIn order to ensure cost-effectiveness, it is packaged using Tube. With the 14-DIP (0.300, 7.62mm) package, additional insulation hardware is no longer required. A reliable performance can be achieved with the supply voltage of 4.75V~5.25V. As a mounting technique, Through Hole has been used. This device has an operating temperature of 0°C~70°C. 1 taps/steps are configured. The device is placed at the location of the terminals at DUAL. Several terminations are provided for unique configurations, including a 14 termination. An operating voltage of 5V is applied to the device when it is in operation. It uses SILICON DELAY LINE as a logic type. A supply voltage of 4.75V is sufficient for it to operate. It is acceptable to run it at the maximum voltage of 5.25V. As part of the CMOS family, there are several active components.
DS1013-75 FeaturesSupply voltage at Tube volts
operate supply current at 5V
with SILICON DELAY LINE bits
stay resistance at CMOS
DS1013-75 ApplicationsThere are a lot of Rochester Electronics, LLC
DS1013-75 Delay Lines Timing ICs applications.
Security Systems
Network Hubs, Bridges, and Routers
QDR/QDRII Memory Systems
Multiphase Clock Generation
LCD Televisions
Telecommunications
Digital Test Equipment
Digital Video Projection
Signal Generators and Analyzers
Clock De-Skewing
| Mounting Type | Through Hole |
| Package / Case | 14-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | 0°C~70°C |
| Packaging | Tube |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Terminal Finish | TIN LEAD |
| Voltage - Supply | 4.75V~5.25V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 5V |
| Terminal Pitch | 2.54mm |
| Time@Peak Reflow Temperature-Max (s) | 20 |
| JESD-30 Code | R-PDIP-T14 |
| Function | Multiple, NonProgrammable |
| Qualification Status | COMMERCIAL |
| Supply Voltage-Max (Vsup) | 5.25V |
| Supply Voltage-Min (Vsup) | 4.75V |
| Family | CMOS |
| Output Polarity | TRUE |
| Logic IC Type | SILICON DELAY LINE |
| Number of Taps/Steps | 1 |
| Number of Independent Delays | 3 |
| Delay to 1st Tap | 75ns |
| Programmable Delay Line | NO |
| Total Delay-Nom (td) | 75 ns |
| Length | 19.05mm |
| Height Seated (Max) | 4.572mm |
| Width | 7.62mm |
| RoHS Status | Non-RoHS Compliant |
| Mount | Through Hole |
| Published | 1999 |
| JESD-609 Code | e3 |
| Terminal Finish | MATTE TIN |
| Peak Reflow Temperature (Cel) | 260 |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | DS1013 |
| Qualification Status | Not Qualified |
| Lead Free | Contains Lead |
DS1013-75 Datasheet
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