EPM7192EGI160-15 OverviewThis network has 192macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).You can find it in package 160-BPGA.As a result, it has 124 I/O ports programmed.160 terminations have been programmed into the device.Its terminal position is PERPENDICULAR.It is powered by a voltage of 5V volts.Package the chip by Tray.In order to ensure the reliability of the device, it is designed to operate at a temperature of [0].Chips should be mounted by Through Hole.In terms of FPGAs, it belongs to the MAX® 7000 series.This device can also display CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V.The 3750 gates serve as building blocks for digital circuits.This logic block consists of 12 logic elements.5.5V represents the maximal supply voltage (Vsup).Ensure that the supply voltage (Vsup) exceeds 4.5V.This device should not have an clock frequency greater than 76.9MHz.
EPM7192EGI160-15 Features160-BPGA package
124 I/Os
The operating temperature of -40°C~85°C TA
EPM7192EGI160-15 ApplicationsThere are a lot of Intel
EPM7192EGI160-15 CPLDs applications.
Discrete logic functions
Bootloaders for FPGAs
Address decoders
Custom state machines
Digital systems
Portable digital devices
Handheld digital devices
Battery operated portable devices
Complex programmable logic devices
Digital designs
| Mounting Type | Through Hole |
| Package / Case | 160-BPGA |
| Surface Mount | NO |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tray |
| Series | MAX® 7000 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 160 |
| ECCN Code | EAR99 |
| Additional Feature | CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| HTS Code | 8542.39.00.01 |
| Terminal Position | PERPENDICULAR |
| Terminal Form | PIN/PEG |
| Supply Voltage | 5V |
| Terminal Pitch | 2.54mm |
| JESD-30 Code | S-CPGA-P160 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Programmable Type | EE PLD |
| Number of I/O | 124 |
| Clock Frequency | 76.9MHz |
| Propagation Delay | 15 ns |
| Number of Gates | 3750 |
| Output Function | MACROCELL |
| Number of Macro Cells | 192 |
| Voltage Supply - Internal | 4.5V~5.5V |
| Delay Time tpd(1) Max | 15ns |
| Number of Logic Elements/Blocks | 12 |
| Length | 39.624mm |
| Height Seated (Max) | 5.34mm |
| Width | 39.624mm |
EPM7192EGI160-15 Datasheet
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