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The LPC2364FET100,551 is a Single-chip 16-bit/32-bit microcontroller that combines the microcontroller with up to 512 kB of embedded high-speed flash memory.
ARM7TDMI-S processor, running at up to 72 MHz
Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high-performance CPU access.
8 kB/32 kB of SRAM on the ARM local bus for high-performance CPU access.
16 kB SRAM for Ethernet interface. Can also be used as general-purpose SRAM.
8 kB SRAM for general-purpose DMA use is also accessible by USB.
Dual Advanced High-performance Bus (AHB) system that provides for simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP serial interfaces, the I2S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port, as well as for memory-to-memory transfers.
Standard ARM test/debug interface for compatibility with existing tools.
The emulation trace module supports real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Four reduced power modes: idle, sleep, power-down, and deep power-down.
Four external interrupt inputs are configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt).
Two independent power domains allow fine tuning of power consumption based on needed features.
Industrial control
Medical systems
Protocol converter
Communications
| Pin Count | 100 |
| RoHS Status | Non-RoHS Compliant |
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