XC2C256-6FT256C OverviewThere are 256 macro cells in the network, which are high-power cell sites that provide radio coverage (tower, antenna, or mast) for a mobile phone network.It is part of the 256-LBGA package.The device has 184 inputs and outputs.There are 256 terminations programmed into the device.As the terminal position of this electrical part is BOTTOM, it serves as an important access point for passengers or freight.Power is supplied by a voltage of 1.8V volts.The chip should be packaged by Tray.The temperature at which it operates is set to 0°C~70°C TA in order to ensure its reliability.Surface Mount should be used for mounting the chip.The CoolRunner II series comprises this type of FPGA.It is programmed with 256 pins.The device can also be used to find REAL DIGITAL DESIGN TECHNOLOGY.The XC2C256 indicates that related parts can be found.It is possible to construct digital circuits using 6000 gates, which are devices that serve as building blocks.High efficiency requires a voltage supply of 1.8V.Surface Mount mounts this electronic component.Vsup reaches 1.9V as the maximum supply voltage.It is recommended that the maximum frequency be less than 256MHz.In order to form a fundamental building block, there are 16logic elements/cells.
XC2C256-6FT256C Features256-LBGA package
184 I/Os
The operating temperature of 0°C~70°C TA
256 pin count
XC2C256-6FT256C ApplicationsThere are a lot of Xilinx Inc.
XC2C256-6FT256C CPLDs applications.
Interface bridging
I/O expansion
Discrete logic functions
Bootloaders for FPGAs
Address decoders
Custom state machines
Digital systems
Portable digital devices
Handheld digital devices
Battery operated portable devices
| Factory Lead Time | 10 Weeks |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 256-LBGA |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Series | CoolRunner II |
| Published | 2001 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 256 |
| ECCN Code | EAR99 |
| Additional Feature | REAL DIGITAL DESIGN TECHNOLOGY |
| HTS Code | 8542.39.00.01 |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 1mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | XC2C256 |
| Pin Count | 256 |
| Qualification Status | Not Qualified |
| Operating Supply Voltage | 1.8V |
| Supply Voltage-Max (Vsup) | 1.9V |
| Programmable Type | In System Programmable |
| Number of I/O | 184 |
| Propagation Delay | 6 ns |
| Number of Logic Elements/Cells | 16 |
| Number of Gates | 6000 |
| Max Frequency | 256MHz |
| Speed Grade | 6 |
| Output Function | MACROCELL |
| Number of Macro Cells | 256 |
| JTAG BST | YES |
| Voltage Supply - Internal | 1.7V~1.9V |
| Delay Time tpd(1) Max | 5.7ns |
| Length | 17mm |
| Height Seated (Max) | 1.55mm |
| Width | 17mm |
| RoHS Status | Non-RoHS Compliant |