XC2C256-6VQ100C OverviewThis network has 256macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).You can find it in package 100-TQFP.As a result, it has 80 I/O ports programmed.100 terminations have been programmed into the device.Its terminal position is QUAD.It is powered by a voltage of 1.8V volts.Package the chip by Tray.In order to ensure the reliability of the device, it is designed to operate at a temperature of [0].Chips should be mounted by Surface Mount.In terms of FPGAs, it belongs to the CoolRunner II series.It has 100 pins programmed.This device can also display REAL DIGITAL DESIGN TECHNOLOGY.Its related parts can be found in the [0].The 6000 gates serve as building blocks for digital circuits.It is recommended that the supply voltage be kept at 1.8Vto maximize efficiency.The electronic component is mounted by Surface Mount.There are 100 pins on the device.1.9V represents the maximal supply voltage (Vsup).The maximum frequency should not exceed 256MHz.A fundamental building block of logic consists of 16 logic elements/cells.
XC2C256-6VQ100C Features100-TQFP package
80 I/Os
The operating temperature of 0°C~70°C TA
100 pin count
100 pins
XC2C256-6VQ100C ApplicationsThere are a lot of Xilinx Inc.
XC2C256-6VQ100C CPLDs applications.
Discrete logic functions
Bootloaders for FPGAs
Address decoders
Custom state machines
Digital systems
Portable digital devices
Handheld digital devices
Battery operated portable devices
Complex programmable logic devices
Digital designs
| Factory Lead Time | 10 Weeks |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 100-TQFP |
| Number of Pins | 100 |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Series | CoolRunner II |
| Published | 2001 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 100 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn85Pb15) |
| Additional Feature | REAL DIGITAL DESIGN TECHNOLOGY |
| HTS Code | 8542.39.00.01 |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 225 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | XC2C256 |
| Pin Count | 100 |
| Qualification Status | Not Qualified |
| Operating Supply Voltage | 1.8V |
| Supply Voltage-Max (Vsup) | 1.9V |
| Programmable Type | In System Programmable |
| Number of I/O | 80 |
| Propagation Delay | 6 ns |
| Number of Logic Elements/Cells | 16 |
| Number of Gates | 6000 |
| Max Frequency | 256MHz |
| Speed Grade | 6 |
| Output Function | MACROCELL |
| Number of Macro Cells | 256 |
| JTAG BST | YES |
| Voltage Supply - Internal | 1.7V~1.9V |
| Delay Time tpd(1) Max | 5.7ns |
| Length | 14mm |
| Height Seated (Max) | 1.2mm |
| Width | 14mm |
| RoHS Status | Non-RoHS Compliant |