XCR3128XL-10CS144I Overview 128 macrocells are present in the mobile phone network, which offer radio coverage from a high-power cell tower, antenna, or mast.The item is enclosed in a 144-TFBGA, CSPBGA package.The device is programmed with 108 I/O ports.It is programmed to terminate devices at 144.There is a BOTTOM terminal position on the electrical part in question.The device is powered by a voltage of 3.3V volts.It is recommended that the chip be packaged by Bulk.Ensure its reliability by operating at -40°C~85°C TA.It is recommended to mount the chip by Surface Mount.FPGAs belonging to the CoolRunner XPLA3 series contain this type of chip.With 144 pins programmed, the chip is ready to use.When using this device, YES is also available.3000 gates are used to construct digital circuits.If high efficiency is desired, the supply voltage should be kept at 3.3V.It is recommended that data be stored in EEPROM.The pins are 144.Initially, the maximum supply voltage (Vsup) is 3.6V.It is important to make sure that the maximum frequency is less than 95MHz.An elementary building block consists of 8logic elements/cells.
XCR3128XL-10CS144I Features144-TFBGA, CSPBGA package
108 I/Os
The operating temperature of -40°C~85°C TA
144 pin count
144 pins
XCR3128XL-10CS144I ApplicationsThere are a lot of Xilinx Inc.
XCR3128XL-10CS144I CPLDs applications.
Digital systems
Portable digital devices
Handheld digital devices
Battery operated portable devices
Complex programmable logic devices
Digital designs
Field programmable gate
Address decoding
D/T registers and latches
Synchronous or asynchronous mode
| Factory Lead Time | 10 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 144-TFBGA, CSPBGA |
| Surface Mount | YES |
| Number of Pins | 144 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Bulk |
| Series | CoolRunner XPLA3 |
| Published | 1996 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 144 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn63Pb37) |
| Additional Feature | YES |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 144 |
| Operating Supply Voltage | 3.3V |
| Supply Voltage-Max (Vsup) | 3.6V |
| Programmable Type | In System Programmable (min 1K program/erase cycles) |
| Number of I/O | 108 |
| Memory Type | EEPROM |
| Propagation Delay | 10 ns |
| Turn On Delay Time | 10 ns |
| Number of Logic Elements/Cells | 8 |
| Number of Gates | 3000 |
| Max Frequency | 95MHz |
| Speed Grade | 10 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| Voltage Supply - Internal | 2.7V~3.6V |
| Delay Time tpd(1) Max | 9.1ns |
| Length | 12mm |
| Height Seated (Max) | 1.2mm |
| Width | 12mm |
| Radiation Hardening | No |
| RoHS Status | Non-RoHS Compliant |