The ADSP-21060KB-160 SHARC®—Super Harvard Architecture Computer—is a 32-bit signal processing microcomputer offering high DSP performance levels. The ADSP-21060KB-160 builds on the ADSP-21000 DSP core to form a complete system-on-a-chip,

adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus. Fabricated in a high-speed, low-power CMOS process, the ADSP-21060KB-160 has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle.

40 MIPS, 25 ns instruction rate, single-cycle instruction execution

120 MFLOPS peak, 80 MFLOPS sustained performance

Dual data address generators with modulo and bit-reverse addressing)

Efficient program sequencing with zero-overhead looping: Single-cycle loop setup

Automotive 

Body electronics & lighting 

Communications equipment 

Broadband fixed line access 

Personal electronics 

Connected peripherals & printers