SI5345D-D-GM Overview
As a clock IC, it is packaged by the Tray method. The 64-VFQFN Exposed Pad package embeds this Clock PLL. The frequency generator is capable of withstanding a maximum temperature of 260 during reflowing. As you can see, it consists of 64 terminations. Basically, this time clock generator needs a voltage of 1.8V. There is a Clock PLL called LVCMOS, LVDS, LVPECL, Crystal which is designed to be the input to this clock generator. Using 1 circuits, the electronic part's full performance can be accessed. RF synthesizers based on this clock provide frequencies up to 350MHz maximum. A Surface Mount-shaped electrical component makes it convenient to mount on a panel. Incorporating CLOCK GENERATOR, PROCESSOR SPECIFIC uPs/uCs/Peripheral ICs, this RF synthesizer features CLOCK GENERATOR, PROCESSOR SPECIFIC. There should be 1.71V~3.47V provided with this RF synthesizer. As determined by the test statistics, the ambient temperature should be set to -40°C~85°C. In this case, we are dealing with a frequency synthesizer that can be used with CML, HCSL, LVCMOS, LVDS, LVPECL logic levels. ALSO REQUIRES 3.3V SUPPLY is included in this frequency generator to enhance clock signal output.
SI5345D-D-GM Features
Available in the 64-VFQFN Exposed Pad
Supply voltage of 1.8V

SI5345D-D-GM Applications
There are a lot of Silicon Labs
SI5345D-D-GM Clock Generators applications.

Picocells, femtocells and small cells
Sampling clocks for ADC and DAC
1 Gigabit Ethernet
10 Gigabit Ethernet
FPGA and processor clocks
Line cards used in telephone exchange
Fiber Channel
PCI express cards
Infotainment systems
Medical equipment

Factory Lead Time	6 Weeks
Mounting Type	Surface Mount
Package / Case	64-VFQFN Exposed Pad
Surface Mount	YES
Operating Temperature	-40°C~85°C
Packaging	Tray
Published	2016
JESD-609 Code	e4
Part Status	Active
Moisture Sensitivity Level (MSL)	2 (1 Year)
Number of Terminations	64
ECCN Code	EAR99
Terminal Finish	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
Additional Feature	ALSO REQUIRES 3.3V SUPPLY
Voltage - Supply	1.71V~3.47V
Terminal Position	QUAD
Terminal Form	NO LEAD
Peak Reflow Temperature (Cel)	260
Supply Voltage	1.8V
Terminal Pitch	0.5mm
Time@Peak Reflow Temperature-Max (s)	40
Output	CML, HCSL, LVCMOS, LVDS, LVPECL
JESD-30 Code	S-XQCC-N64
Number of Circuits	1
uPs/uCs/Peripheral ICs Type	CLOCK GENERATOR, PROCESSOR SPECIFIC
Frequency (Max)	350MHz
Input	LVCMOS, LVDS, LVPECL, Crystal
Ratio - Input:Output	5:10
PLL	Yes
Differential - Input:Output	Yes/Yes
Divider/Multiplier	Yes/No
Length	9mm
Height Seated (Max)	0.9mm
Width	9mm
RoHS Status	Non-RoHS Compliant