XC2C64A-7QFG48C Overview64 macrocells exist, which are cells in a mobile phone network that are primarily composed of high-power towers, antennas, or masts.A 48-VFQFN Exposed Pad package contains the item.This device has 37 I/O ports programmed into it.It is programmed that device terminations will be 48 .The terminal position of this electrical component is QUAD.A voltage of 1.8V is used as the power supply for this device.It is recommended to package the chip by Tray.During operation, the operating temperature is kept at 0°C~70°C TA to ensure its reliability.Mount the chip by Surface Mount.This type of FPGA is a part of the CoolRunner II series.Chips are programmed with 48 pins.If this device is used, you will also be able to find REAL DIGITAL DESIGN TECHNOLOGY.There are related parts in XC2C64A.In digital circuits, there are 1500 gates, which act as a basic building block.If high efficiency is to be achieved, the supply voltage should be maintained at 1.8V.Data storage is performed using ROMless.In this case, Surface Mount is used to mount the electronic component.The 48 pins are designed into the board.In order to ensure proper operation, a maximum supply voltage (Vsup) of 1.9V is required.Ideally, the maximal frequency should be lower than 159MHz Hz.The fundamental building block consists of 4 logic elements/cells.
XC2C64A-7QFG48C Features48-VFQFN Exposed Pad package
37 I/Os
The operating temperature of 0°C~70°C TA
48 pin count
48 pins
XC2C64A-7QFG48C ApplicationsThere are a lot of Xilinx Inc.
XC2C64A-7QFG48C CPLDs applications.
Address decoders
Custom state machines
Digital systems
Portable digital devices
Handheld digital devices
Battery operated portable devices
Complex programmable logic devices
Digital designs
Field programmable gate
Address decoding
| Factory Lead Time | 10 Weeks |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 48-VFQFN Exposed Pad |
| Number of Pins | 48 |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Series | CoolRunner II |
| Published | 2001 |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 48 |
| ECCN Code | EAR99 |
| Terminal Finish | Matte Tin (Sn) |
| Additional Feature | REAL DIGITAL DESIGN TECHNOLOGY |
| Terminal Position | QUAD |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | XC2C64A |
| Pin Count | 48 |
| Qualification Status | Not Qualified |
| Operating Supply Voltage | 1.8V |
| Supply Voltage-Max (Vsup) | 1.9V |
| Programmable Type | In System Programmable |
| Number of I/O | 37 |
| Memory Type | ROMless |
| Propagation Delay | 7.5 ns |
| Number of Logic Elements/Cells | 4 |
| Number of Gates | 1500 |
| Max Frequency | 159MHz |
| Speed Grade | 7 |
| Output Function | MACROCELL |
| Number of Macro Cells | 64 |
| JTAG BST | YES |
| Voltage Supply - Internal | 1.7V~1.9V |
| Delay Time tpd(1) Max | 6.7ns |
| Height Seated (Max) | 1mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |