XCR3128XL-7CS144I OverviewThere are 128 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).It is contained in package [0].The device is programmed with 108 I/Os.Devices are programmed with terminations of 144.This electrical part has a terminal position of BOTTOM, which serves as an important point of access for passengers and freight.The power supply voltage is 3.3V.Bulk is the packaging method.To ensure reliability, the device operates at a temperature of -40°C~85°C TA.It is recommended that the chip be mounted by Surface Mount.As part of the CoolRunner XPLA3 series, it is a type of FPGA.144 pins are programmed on the chip.This device is also capable of displaying YES.As a building block for digital circuits, there are 3000 gates.A total of 8 logic elements/blocks are present.There is 3/3.3V power supply available for it.3.6V is the maximum supply voltage (Vsup).In order to operate properly, the supply voltage (Vsup) should be greater than 2.7V.It should not exceed 119MHz in terms of clockfrequency.
XCR3128XL-7CS144I Features144-TFBGA, CSPBGA package
108 I/Os
The operating temperature of -40°C~85°C TA
144 pin count
3/3.3V power supplies
XCR3128XL-7CS144I ApplicationsThere are a lot of Xilinx Inc.
XCR3128XL-7CS144I CPLDs applications.
Timing control
Interface bridging
I/O expansion
Discrete logic functions
Bootloaders for FPGAs
Address decoders
Custom state machines
Digital systems
Portable digital devices
Handheld digital devices
| Factory Lead Time | 10 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 144-TFBGA, CSPBGA |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Bulk |
| Series | CoolRunner XPLA3 |
| Published | 1996 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 144 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn63Pb37) |
| Additional Feature | YES |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 144 |
| JESD-30 Code | S-PBGA-B144 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3/3.3V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Programmable Type | In System Programmable (min 1K program/erase cycles) |
| Number of I/O | 108 |
| Clock Frequency | 119MHz |
| Propagation Delay | 7.5 ns |
| Number of Gates | 3000 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| Voltage Supply - Internal | 2.7V~3.6V |
| Delay Time tpd(1) Max | 7ns |
| Number of Logic Elements/Blocks | 8 |
| Length | 12mm |
| Height Seated (Max) | 1.2mm |
| Width | 12mm |
| RoHS Status | Non-RoHS Compliant |