XCR3128XL-10CS144C OverviewThe mobile phone network has 128 macro cells, which are cells that provide radio coverage from high-power cell sites (towers, antennas, or masts).In the 144-TFBGA, CSPBGA package, you will find it.In this case, there are 108 I/Os programmed.144 terminations are programmed into the device.This electrical component has a terminal position of BOTTOM.An electrical supply voltage of 3.3V is used to power it.Bulk should be used to package the chip.Due to its reliability, it is operated at a temperature of 0°C~70°C TA.There should be a Surface Mount on the chip.The FPGA belongs to the CoolRunner XPLA3 series.A chip with 144 pins is programmed.This device also displays YES.A digital circuit can be constructed using 3000 gates.In order to achieve high efficiency, the supply voltage should be maintained at 3.3V.In this case, EEPROM will be used to store the data.The device has a pinout of 144.There is a maximum supply voltage (Vsup) of 3.6V.It should be below 95MHz at the maximal frequency.Fundamental building blocks consist of 8 logic elements/cells.
XCR3128XL-10CS144C Features144-TFBGA, CSPBGA package
108 I/Os
The operating temperature of 0°C~70°C TA
144 pin count
144 pins
XCR3128XL-10CS144C ApplicationsThere are a lot of Xilinx Inc.
XCR3128XL-10CS144C CPLDs applications.
I/O expansion
Discrete logic functions
Bootloaders for FPGAs
Address decoders
Custom state machines
Digital systems
Portable digital devices
Handheld digital devices
Battery operated portable devices
Complex programmable logic devices
| Factory Lead Time | 10 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 144-TFBGA, CSPBGA |
| Surface Mount | YES |
| Number of Pins | 144 |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Bulk |
| Series | CoolRunner XPLA3 |
| Published | 1996 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 144 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn63Pb37) |
| Additional Feature | YES |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 144 |
| Operating Supply Voltage | 3.3V |
| Supply Voltage-Max (Vsup) | 3.6V |
| Programmable Type | In System Programmable (min 1K program/erase cycles) |
| Number of I/O | 108 |
| Memory Type | EEPROM |
| Propagation Delay | 10 ns |
| Turn On Delay Time | 10 ns |
| Number of Logic Elements/Cells | 8 |
| Number of Gates | 3000 |
| Max Frequency | 95MHz |
| Speed Grade | 10 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| Voltage Supply - Internal | 3V~3.6V |
| Delay Time tpd(1) Max | 9.1ns |
| Length | 12mm |
| Height Seated (Max) | 1.2mm |
| Width | 12mm |
| Radiation Hardening | No |
| RoHS Status | Non-RoHS Compliant |